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ltm8052 1 8052fa typical a pplica t ion fea t ures descrip t ion 36v in , 5a, 2-quadrant cvcc step-down module regulator the lt m ? 8052 is a 36v in , 5a , 2-quadrant constant- voltage, constant-current ( cvcc) step-down module ? regulator. included in the package are the switching controller, power switches, inductor and support components. operating over an input voltage range of 6 v to 36 v, the ltm8052 supports an output voltage range of 1.2 v to 24 v. the ltm8052 is able to sink or source current to maintain voltage regulation up to the positive and negative current limits. this output current limit can be set by a control voltage, a single resistor or a thermistor. the ltm8052 is packaged in a thermally-enhanced, com- pact (11.25 mm 15 mm 2.82 mm) rohs compliant, overmolded land grid array ( lga) package suitable for au- tomated assembly by standard surface mount equipment. part number best for ltm8052 sinking and sourcing output current ltm8026 sourcing more than 3a of output current. (less than 3a maximum consider ltm8025.) 5a, 2.5v (2-quadrant) module voltage regulator a pplica t ions n complete step-down switch mode power supply n cvcc: constant-voltage constant-current n 2-quadrant: sources and sinks output current n adjustable output current n wide input voltage range: 6v to 36v n 1.2 v to 24v output voltage n forced continuous operation n selectable switching frequency: 100khz to 1mhz n (e4) rohs compliant package with gold pad finish n programmable soft-start n tiny, low profile (11.25mm 15mm 2.82mm) sur face mount lga package n constant-frequency voltage regulation even at no load n peltier driver n battery tester n battery/supercap charging and cell balancing n motor drive power regulator n high power led drive output voltage vs output current v in run 510k ss ltm8052 sync 100f 330f *input voltage protection may be necessary when the ltm8052 is sinking current (see applications information) 8052 ta01a 10f v in * 6v to 36v v out 2.5v 5a comp v out v ref ctl_i ctl_t rt gnd 90.9k 9.09k adj optional input protection + load current (a) ?10 2.0 2.5 3.5 5 8052 ta01b 1.5 1.0 ?5 0 10 0.5 0 3.0 output voltage (v) l, lt , lt c , lt m , linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7199560, 7321203 and others pending.
ltm8052 2 8052fa p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ............................................................................ 40 v ad j , rt, comp , ctl _i, ctl _t, v ref ........................... 3v v out .......................................................................... 25 v run , sync , ss ........................................................... 6 v current into run pin ............................................ 10 0 a internal operating temperature range .. C 40 c to 125 c solder temperature ............................................... 25 0 c storage temperature .............................. C55 c to 125 c (note 1) bank 3 sync run ctl_t ctl_i v ref rt comp ss adj bank 1 a b c d e f lga package 81-lead (15mm 11.25mm 2.82mm) top view g h j k l bank 2 gnd v out 8 7 6 5 4 3 2 1 v in t jmax = 125c, ja = 18.6c/w, jc(bottom) = 5.4c/w, jb = 5.6c/w, jc(top) = 10.8c/w pcb weight = 1.4 grams, values derived from a 4-layer 7.62cm 7.62cm o r d er i n f or m a t ion lead free finish tray part marking* package description temperature range ? ltm8052ev#pbf ltm8052ev#pbf ltm8052v 81-lead (15mm 11.25mm 2.82mm) lga C40c to 125c ltm8052iv#pbf ltm8052iv#pbf ltm8052v 81-lead (15mm 11.25mm 2.82mm) lga C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ ? refer to note 3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c. run = 3v, unless otherwise noted. (note 3) parameter conditions min typ max units minimum input voltage l 6 v output dc voltage i out = 1a, r adj open i out = 1a, r adj = 499 1.2 24 v v output dc current ctl_t, ctl_i = 1.5v C6 5 a quiescent current into v in v in = 12v, run = 0v v in = 12v, no load 0.1 17 3 30 a ma line regulation 6v < v in < 36v, i out = 1a 0.1 % load regulation v in = 12v, 0a < i out < 5a 0.7 % output rms voltage ripple v in = 12v, i out = 4.5a 10 mv switching frequency r t = 40.2k r t = 453k 1000 100 khz khz voltage at adj pin l 1.16 1.19 1.22 v current out of adj pin adj = 0v, v out = 1v 100 a run pin current run = 1.45v 5.5 a
ltm8052 3 8052fa e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c. run = 3v, unless otherwise noted. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this module regulator includes overtemperature protection that is intended to protect the device during momentary overload conditions. internal temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum internal operating junction temperature may impair device reliability. note 3: the ltm8052e is guaranteed to meet performance specifications from 0c to 125c internal operating temperature. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm8052i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. parameter conditions min typ max units run threshold voltage (falling) 1.49 1.55 1.61 v run input hysteresis 160 mv ctl_i control range 0 1.5 v ctl_i pin current 1.5 a ctl_i positive current limit ctl_i = 1.5v ctl_i = 0.75v 5.1 2.24 5.6 2.8 6.1 3.36 a a ctl_i negative current limit ctl_i = 1.5v ctl_i = 0.75v C8.5 C5.7 C7.7 C5.1 C6.9 C4.5 a a ctl_t control range 0 1.5 v ctl_t pin current 1.5 a ctl_t positive current limit ctl_t = 1.5v ctl_t = 0.75v 5.1 2.24 5.6 2.8 6.1 3.36 a a ctl_t negative current limit ctl_t = 1.5v ctl_t = 0.75v C8.5 C5.5 C7.7 C4.9 C6.9 C4.3 a a v ref voltage 0.5ma load 1.93 2 2.04 v ss pin current 11 a sync input low threshold f sync = 400khz 0.6 v sync input high threshold f sync = 400khz 1.2 v sync bias current sync = 0v 1 a typical p er f or m ance c harac t eris t ics 1.2v out efficiency 1.5v out efficiency 1.8v out efficiency t a = 25c, unless otherwise noted. output current (a) 0 efficiency (%) 65 70 75 3 5 8052 g01 60 55 50 1 2 4 80 85 90 6v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g02 60 55 50 10 2 4 80 85 90 6v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g03 60 55 50 10 2 4 80 85 95 90 6v in 12v in 24v in 36v in
ltm8052 4 8052fa typical p er f or m ance c harac t eris t ics 2.5v out efficiency 3.3v out efficiency 5v out efficiency 8v out efficiency 12v out efficiency 18v out efficiency 24v out efficiency C3.3v out efficiency C5v out efficiency t a = 25c, unless otherwise noted. output current (a) efficiency (%) 65 70 75 3 5 8052 g04 60 55 50 10 2 4 80 85 95 90 6v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g05 60 55 50 10 2 4 80 85 95 90 6v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g06 60 55 50 10 2 4 80 85 100 95 90 8v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g07 60 55 50 10 2 4 80 85 100 95 90 10v in 12v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g08 60 55 50 10 2 4 80 85 100 95 90 15v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g09 60 55 50 10 2 4 80 85 100 95 90 22v in 24v in 36v in output current (a) efficiency (%) 65 70 75 3 4 8052 g10 60 55 50 1 0 2 80 85 100 95 90 28v in 36v in output current (a) efficiency (%) 65 70 75 3 5 8052 g11 60 55 50 10 2 4 80 85 90 12v in 24v in 32.5v in output current (a) efficiency (%) 65 70 75 3 5 8052 g12 60 55 50 10 2 4 80 85 90 12v in 24v in 31v in
ltm8052 5 8052fa typical p er f or m ance c harac t eris t ics C8v out efficiency C12v out efficiency input current vs output current 1.2v out input current vs output current 1.5v out input current vs output current 1.8v out input current vs output current 2.5v out t a = 25c, unless otherwise noted. output current (a) efficiency (%) 65 70 75 3 5 8052 g13 60 55 50 10 2 4 80 85 90 12v in 24v in 28v in output current (a) efficiency (%) 65 70 75 3 5 8052 g14 60 55 50 10 2 4 80 85 90 12v in 24v in output current (a) ?8 input current (a) 0.8 ?2 8052 g15 0.2 ?0.2 ?6 ?4 0 ?0.4 ?0.6 1.0 0.6 0.4 0 2 4 6 12v in 24v in 36v in output current (a) ?8 input current (a) 0.8 ?2 8052 g16 0.2 ?0.2 ?6 ?4 0 ?0.4 ?0.6 1.0 0.6 0.4 0 2 4 6 12v in 24v in 36v in output current (a) ?8 ?0.8 input current (a) ?0.6 ?0.2 0 0.2 1.2 0.6 ?4 0 2 8052 g17 ?0.4 0.8 1.0 0.4 ?6 ?2 4 6 12v in 24v in 36v in output current (a) ?8 0.5 1.0 2.0 ?2 2 8052 g18 0 ?0.5 ?6 ?4 0 4 6 ?1.0 ?1.5 1.5 input current (a) 12v in 24v in 36v in input current vs output current 3.3v out input current vs output current 5v out input current vs output current 8v out output current (a) ?8 ?2 input current (a) ?1 0 1 2 ?6 ?4 ?2 0 8052 g19 2 4 6 12v in 24v in 36v in output current (a) ?8 input current (a) 1 2 3 ?2 2 8052 g20 0 ?1 ?6 ?4 0 4 6 ?2 ?3 12v in 24v in 36v in output current (a) ?8 ?5 input current (a) ?4 ?2 ?1 0 5 2 ?4 0 2 8052 g21 ?3 3 4 1 ?6 ?2 4 6 12v in 24v in 36v in
ltm8052 6 8052fa typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. input current vs output current 12v out input current vs input voltage (output shorted) input current vs output current C3.3v out input current vs output current C5v out input current vs output current C8v out input current vs output current C12v out minimum required input running voltage vs negative output voltage input current vs output current 18v out input current vs output current 24v out input voltage (v) 0 400 500 700 30 8052 g25 300 200 10 20 40 100 0 600 input current (ma) output voltage (v) 0 0 input voltage (v) 5 10 15 20 25 ?5 ?10 8052 g30 ?15 i out = 4a i out = 3a i out = 2a i out = 1a output current (a) ?6 4 3 2 1 0 ?1 ?2 ?3 0 4 8052 g22 ?4 ?2 2 6 input current (a) 24v in 36v in output current (a) ?6 ?4 input current (a) ?3 ?1 0 1 2 5 8052 g23 ?2 ?2 ?4 4 0 6 2 3 4 24v in 36v in output current (a) ?5 ?4 ?3 input current (a) ?2 0 1 2 4 ?4 0 2 8052 g24 ?1 3 ?1 4 5 ?3 ?2 1 3 36v in output current (a) ?1.5 input current (a) ?0.5 0.5 1.5 ?1.0 0 1.0 ?4 ?2 0 2 8052 g26 5 ?5?6 ?3 ?1 1 3 4 24v in 12v in output current (a) ?6 ?3 input current (a) ?2 ?1 0 1 2 3 ?4 ?2 0 2 8052 g28 4 24v in 12v in output current (a) ?6 ?2.5 input current (a) ?2.0 ?1.0 ?0.5 0 ?2 2 4 2.0 8052 g29 ?1.5 ?4 0 0.5 1.0 1.5 24v in output current (a) ?6 input current (a) 0 1 2 8052 g27 ?1 ?2 ?4 ?2 0 4 2 24v in 12v in
ltm8052 7 8052fa typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. minimum required input running voltage vs output voltage, i out = 5a minimum required input voltage vs load 3.3v out and below minimum required input voltage vs load 5v out minimum required input voltage vs load 8v out minimum required input voltage vs load 12v out minimum required input voltage vs load 18v out output voltage (v) 0 0 input voltage (v) 5 10 15 20 30 5 10 15 20 8052 g31 25 30 25 load current (a) 0 input voltage (v) 6.0 6.2 6.4 4 8052 g32 5.8 5.6 1 2 3 5 load current (a) 0 input voltage (v) 6.8 7.2 7.0 4 8052 g33 6.6 6.4 1 2 3 5 load current (a) 0 input voltage (v) 9.4 9.6 10.0 9.8 4 8052 g34 9.2 9.0 1 2 3 5 load current (a) 0 13.2 input voltage (v) 13.4 13.6 13.8 14.0 14.2 14.4 1 2 3 4 8052 g35 5 load current (a) 0 19.0 input voltage (v) 19.5 20.0 20.5 21.0 21.5 1 2 3 4 8052 g36 5 minimum required input voltage vs load 24v out minimum required input voltage vs load C3.3v out minimum required input voltage vs load C5v out load current (a) 0 25.5 input voltage (v) 26.0 26.5 27.0 27.5 28.0 1 2 3 4 8052 g37 5 load current (a) 0 25 30 35 4 8052 g38 20 15 1 2 3 5 10 5 0 input voltage (v) to start to run load current (a) 0 25 30 35 4 8052 g39 20 15 1 2 3 5 10 5 0 input voltage (v) to start to run
ltm8052 8 8052fa minimum required input voltage vs load C8v out minimum required input voltage vs load C12v out temperature rise vs load current 2.5v out temperature rise vs load current 3.3v out temperature rise vs load current 12v out temperature rise vs load current 5v out temperature rise vs load current 18v out temperature rise vs load current 8v out temperature rise vs load current 24v out typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. load current (a) 0 25 30 4 8052 g40 20 15 1 2 3 5 10 5 0 input voltage (v) to start to run load current (a) 0 25 30 8052 g41 20 15 1 2 3 4 10 5 0 input voltage (v) to start to run load current (a) 0 50 60 4 8052 g42 40 30 1 2 3 5 20 10 0 temperature rise (c) 36v in 24v in 12v in 6v in load current (a) 0 50 60 4 8052 g43 40 30 1 2 3 5 20 10 0 temperature rise (c) 36v in 24v in 12v in 6v in load current (a) 0 50 70 60 4 8052 g44 40 30 1 2 3 5 20 10 0 temperature rise (c) 36v in 24v in 12v in 7v in load current (a) 0 0 temperature rise (c) 10 30 40 50 2 4 5 90 8052 g45 20 1 3 60 70 80 36v in 24v in 12v in load current (a) 0 100 120 4 8052 g46 80 60 1 2 3 5 40 20 0 temperature rise (c) 36v in 24v in 15v in load current (a) 0 100 120 4 8052 g47 80 60 1 2 3 5 40 20 0 temperature rise (c) 36v in 24v in load current (a) 0 temperature rise (c) 60 80 100 4 8052 g48 40 20 50 70 90 30 10 0 1 2 3 5 36v in 28v in
ltm8052 9 8052fa temperature rise vs load current C3.3v out temperature rise vs load current C12v out switching frequency vs r t value temperature rise vs load current C5v out temperature rise vs load current C8v out typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. load current (a) 0 50 70 60 4 8052 g49 40 30 1 2 3 5 20 10 0 temperature rise (c) 32.5v in 24v in 12v in load current (a) 0 temperature rise (c) 30 40 50 3 5 8052 g50 20 10 0 1 2 4 60 70 80 31v in 24v in 12v in load current (a) 0 0 temperature rise (c) 10 30 40 50 2 4 5 90 8052 g51 20 1 3 60 70 80 28v in 24v in 12v in load current (a) 0 100 120 8052 g52 80 60 1 2 3 4 40 20 0 temperature rise (c) 24v in 12v in switching frequency (mhz) 0 r t value (k) 300 400 500 0.8 8052 g53 200 100 250 350 450 150 50 0 0.2 0.4 0.6 1.0 ctl_i voltage vs maximum output current, ctl_t = 2v ctl_t voltage vs maximum output current, ctl_i = 2v ctl_i voltage (v) 0 6 4 2 0 ?2 ?4 ?6 ?8 0.75 1.25 8052 g54 0.25 0.5 1 1.5 maximum current (a) ctl_t voltage (v) 0 6 4 2 0 ?2 ?4 ?6 ?8 0.75 1.25 8052 g55 0.25 0.5 1 1.5 maximum current (a)
ltm8052 10 8052fa p in func t ions v out (bank 1): power output pins. apply the output filter capacitor and the output load between these pins and gnd pins. when reverse current is being driven into the ltm8052 s output by the load, the energy is delivered back through the ltm8052 and out to the v in pins. care must be taken to prevent excessive voltage if other devices on the v in bus cannot absorb this energy. see input precautions in the applications information section for more details and circuit suggestions. gnd (bank 2): tie these gnd pins to a local ground plane below the ltm8052 and the circuit components. in most applications, the bulk of the heat flow out of the ltm8052 is through these pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. return the feedback divider ( r adj ) to this net. v in ( bank 3): the v in pins supply current to the ltm8052 s internal regulator and to the internal power switches. this pin must be locally bypassed with an external, low esr capacitor; see table 1 for recommended values. ctl _t ( pin d 8): connect a resistor/ ntc thermistor network to the ctl_t pin to reduce the maximum regulated output current of the ltm8052 in response to temperature. the maximum control voltage is 1.5 v. if this function is not used, tie this pin to v ref . ctl_i ( pin e8): the ctl_i pin reduces the maximum regulated output current of the ltm8052. the maximum control voltage is 1.5 v. if this function is not used, tie this pin to v ref . v ref ( pin f8): buffered 2 v reference capable of 0.5 ma drive. it is valid when v in > 6v and run is active high. rt ( pin g8): the rt pin is used to program the switching frequency of the ltm8052 by connecting a resistor from this pin to ground. the applications information section of the data sheet includes a table to determine the resistance value based on the desired switching frequency. when us- ing the sync function, apply a resistor value equivalent to 20% lower than the clock frequency applied to the sync pin. do not leave this pin open. comp ( pin h8): compensation pin. this pin is generally not used. the ltm8052 is internally compensated, but some rare situations may arise that require a modifica- tion to the control loop. this pin connects directly to the input pwm comparator of the ltm8052. in most cases, no adjustment is necessary. if this function is not used, leave this pin open. ss ( pin j8): soft-start pin. place an external capacitor to ground to ramp the output voltage during start-up condi- tions. the soft-start pin has an 11a charging current. adj ( pin k 8): the ltm8052 regulates its adj pin to 1.19 v. connect the adjust resistor from this pin to ground. the value of r adj is given by the equation: r adj = 11.9 v out ? 1.19 where r adj is in k. run ( pin l6): the run pin acts as an enable pin and turns on the internal circuitry. it may also be used to implement a precision uvlo. see the applications information sec- tion for details. the run pin is internally clamped, so it may be pulled up to a voltage source that is higher than the absolute maximum voltage of 6 v through a resistor, provided the pin current does not exceed 100 a. do not leave this pin open. sync (pin l7): frequency synchronization pin. this pin allows the switching frequency to be synchronized to an external clock. the r t resistor should be chosen to oper- ate the internal clock at 20% lower than the sync pulse frequency. this pin should be grounded when not in use. do not leave this pin floating. when laying out the board, avoid noise coupling to or from the sync trace. see the synchronization section in applications information.
ltm8052 11 8052fa b lock diagra m run 0.2f ss sync v ref ctl_i ctl_t comp gnd rt adj 8026 bd v out v in internal regulator r sense 2.2h 10k 2.2f 10k 2.2nf v in current mode controller o pera t ion the ltm8052 is a standalone nonisolated constant- voltage, constant-current step-down switching dc/dc power sup- ply that can deliver up to 5 a of positive or 6 a of negative output current. this module regulator provides a precisely regulated output voltage programmable via one external resistor from 1.2 v to 24 v. the input voltage range is 6v to 36 v. given that the ltm8052 is a step-down converter, make sure that the input voltage is high enough to support the desired output voltage and load current. the ltm8052 is a 2- quadrant device, meaning that it can both source and sink current in order to regulate its output voltage. most traditional voltage regulators are one quadrant; that is, they only source current. if the load, for whatever reason, forces current into a traditional regulator, the output voltage will typically rise. in a similar situation, the ltm8052 will sink current to keep the output voltage in regulation. it should be clear that the above situation is only possible if the load is providing energy to the ltm8052 output. the ltm8052 will be able to maintain the output voltage at the target regulation point as long as the current from the load does not exceed its negative current limit. if the current does exceed the negative current limit, the ltm8052 output will start to rise. if the output continues to rise, the ltm8052 s output overvoltage protection circuitry will turn off the internal power switches, and the output will be free to rise. if this voltage rises above the ltm8052 input voltage, current will flow through an internal diode, and the output will be clamped to a diode drop above the input.
ltm8052 12 8052fa when the ltm8052 is sinking current, it maintains its output voltage regulation by power conversion, not power dissipation. this means that the energy provided to the ltm8052 is in turn delivered to its input power bus. there must be something on this power bus to accept or use the energy, or the ltm8052s input voltage will rise. left unchecked, the energy can raise the input voltage above the absolute maximum voltage and damage the ltm8052. please see the input precautions section for further details. for applications where only sourcing current ( one quadrant operation) is desired, use ltm8026. the ltm8052 operates in forced continuous mode. this means that the part will not skip cycles when the load approaches zero amps. this may be particularly useful in applications where the synchronization function is used, or any time discontinuous switching is undesirable. the ltm8052 will not operate in forced continuous mode when an input uvlo, output ovlo or minimum duty cycle violation occurs. as shown in the block diagram, the ltm8052 contains a current mode controller, power switches, power inductor, and a modest amount of input and output capacitance. the ltm8052 utilizes fixed frequency, average current mode control to accurately regulate the inductor current, independent from the output voltage. this is an ideal solu- tion for applications requiring a regulated current source. the control loop will regulate the current in the internal inductor. once the output has reached the regulation voltage determined by the resistor from the adj pin to ground, the inductor current will be reduced by the volt- age regulation loop. o pera t ion the output current loop has two control inputs, deter- mined by the voltage at the analog control pins, ctl_i and ctl_t . ctl_i is typically used to set the maximum allowable current output of the ltm8052, while ctl_t is typically used with a ntc thermistor to reduce the output current in response to temperature. the lower of the two analog voltages on ctl_i and ctl_t determines the regulated output current. the analog control range of both the ctl_i and ctl_t pin is from 0 v to 1.5 v. as shown in the typical performance characteristics section, the positive and negative currents are not symmetric. the negative current limit is offset by approximately 2a. the run pin functions as a precision shutdown pin. when the voltage at the run pin is lower than 1.55 v, switch- ing is terminated. below the turn-on threshold, the run pin sinks 5.5 a. this current can be used with a resistor between run and v in to set a hysteresis. during start- up, the ss pin is held low until the part is enabled, after which the capacitor at the soft-start pin is charged with an 11a current source. the ltm8052 is equipped with a thermal shutdown to protect the device during momentary overload conditions. it is set above the 125 c absolute maximum internal tem- perature rating to avoid interfering with normal specified operation, so internal device temperatures will exceed the absolute maximum rating when the overtemperature protection is active. so, continuous or repeated activation of the thermal shutdown may impair device reliability. during thermal shutdown, all switching is terminated and the ss pin is driven low. the switching frequency is determined by a resistor at the rt pin. the ltm8052 may also be synchronized to an external clock through the use of the sync pin.
ltm8052 13 8052fa a pplica t ions i n f or m a t ion for most applications, the design process is straight forward, summarized as follows: 1. look at table 1 and find the row that has the desired input range and output voltage. 2. apply the recommended c in , c out , r adj and r t values. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. bear in mind that the maximum output current is limited by junction temperature, the relationship between the input and output voltage mag- nitude and polarity and other factors. please refer to the table 1. recommended component values and configuration. (t a = 25c. see typical performance characteristics for load conditions) v in v out c in c out ceramic c out electrolytic r adj f optimal r t( optimal ) f max r t(min) 6v to 36v 1.2 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g open 200khz 210k 250khz 169k 6v to 36v 1.5 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 38.3k 300khz 140k 350khz 118k 6v to 36v 1.8 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 19.6k 350khz 118k 400khz 102k 6v to 36v 2.5 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 9.09k 450khz 90.9k 525khz 78.7k 6v to 36v 3.3 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 5.62k 550khz 75.0k 625khz 64.9k 7v to 36v 5 10f, 50v, 1210 100f, 6.3v, 1210 120f , 16v , 27m , os - con, 16svpc120 m 3.09k 600khz 68.1k 700khz 57.6k 10v to 36v 8 10f, 50v, 1210 100f, 10v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.74k 625khz 64.9k 750khz 53.6k 15v to 36v 12 10f, 50v, 1210 47f, 16v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.10k 650khz 61.9k 800khz 49.9k 22v to 36v 18 10f, 50v, 1210 22f, 25v, 1210 47f, 20v, 45m, os -con, 20svps47m 604 675 khz 59.0k 900khz 44.2k 28v to 36v 24 4.7f , 50v , 1210 10f, 50v, 1206 47f, 35v, 30m, os-con, 35svpc47m 523 700khz 57.6k 1mhz 39.2k 9v to 15v 1.2 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g open 200khz 210k 525khz 78.7k 9v to 15v 1.5 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 38.3k 300khz 140k 650khz 61.9k 9v to 15v 1.8 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 19.6k 350khz 118k 800khz 49.9k 9v to 15v 2.5 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 9.09k 450khz 90.9k 1mhz 39.2k 9v to 15v 3.3 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 5.62k 550khz 75.0k 1mhz 39.2k 9v to 15v 5 10f, 50v, 1210 100f, 6.3v, 1210 120f, 16v, 27m, os-con, 16svpc120m 3.09k 600khz 68.1k 1mhz 39.2k 10v to 15v 8 10f, 50v, 1210 100f, 10v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.74k 625khz 64.9k 1mhz 39.2k 18v to 36v 1.2 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g open 200khz 210 k 250 khz 169k 18v to 36v 1.5 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 38.3k 300khz 140k 350khz 118k 18v to 36v 1.8 10f, 50v, 1210 100f, 6.3v, 1210 470f, 6.3v, 9m, chemi-con, apxf6r3ara471mh80g 19.6k 350khz 118k 400khz 102k 18v to 36v 2.5 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 9.09k 450khz 90.9k 525khz 78.7k 18v to 36v 3.3 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 5.62k 550khz 75.0k 625khz 64.9k 18v to 36v 5 10f, 50v, 1210 100f, 6.3v, 1210 120f, 16v, 27m, os-con, 16svpc120m 3.09k 600khz 68.1k 700khz 57.6k 18v to 36v 8 10f, 50v, 1210 100f, 10v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.74k 625khz 64.9k 750khz 53.6k 18v to 36v 12 10f, 50v, 1210 47f, 16v, 1210 120f , 16v , 27m , os - con, 16svpc120 m 1.10k 650khz 61.9k 800khz 49.9k 2.7 v to 32.5 v* C3.3 10f, 50v, 1210 100f, 6.3v, 1210 330f, 4v, 27m, os-con, 4svpc330m 5.62k 550khz 75.0k 625khz 64.9k 2v to 31 v* C5 10f , 50v , 1210 100f, 6.3v, 1210 120f, 16v, 27m, os-con, 16svpc120m 3.09k 600khz 68.1k 700khz 57.6k 2v to 28 v* C8 10f , 50 v , 1210 100f, 10v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.74k 625khz 64.9k 750khz 53.6k 3v to 24 v* C12 10f , 50v , 1210 47f, 16v, 1210 120f, 16v, 27m, os-con, 16svpc120m 1.10k 650khz 61.9k 800khz 49.9k *running voltage. see the typical performance characteristics section for starting requirements. note: an input bulk capacitor is required.
ltm8052 14 8052fa a pplica t ions i n f or m a t ion graphs in the typical performance characteristics section for guidance. the maximum frequency ( and attendant r t value) at which the ltm8052 should be allowed to switch is given in table 1 in the f max column, while the recommended frequency ( and r t value) for optimal efficiency over the given input condition is given in the f optimal column. there are additional conditions that must be satisfied if the synchronization function is used. please refer to the synchronization section for details. capacitor selection considerations the c in and c out capacitor values in table 1 are the minimum recommended values for the associated oper- ating conditions. applying capacitor values below those indicated in table 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if necessary. again, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature, applied voltage and give dependable service. other types, including y5v and z5u have very large temperature and voltage coefficients of capacitance. in an application circuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. many of the output capacitances given in table 1 specify an electrolytic capacitor. ceramic capacitors may also be used in the application, but it may be necessary to use more of them. many high value ceramic capacitors have a large voltage coefficient, so the actual capacitance of the component at the desired operating voltage may be only a fraction of the specified value. also, the very low esr of ceramic capacitors may necessitate additional capacitors for acceptable stability margin. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8052. a ceramic input capacitor combined with trace or cable inductance forms a high q ( under damped) tank circuit. if the ltm8052 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possi- bly exceeding the devices rating. this situation is easily avoided; see the hot plugging safely section. programming switching frequency the ltm8052 has an operational switching frequency range between 100 khz and 1 mhz. this frequency is programmed with an external resistor from the rt pin to ground. do not leave this pin open under any circumstance . see table? 2 for resistor values and the corresponding switching frequencies. table 2. r t resistor values and their resultant switching frequencies switching frequency (mhz) r t (k) 1 39.2 0.75 53.6 0.5 82.5 0.3 140 0.2 210 0.1 453 in addition, the typical performance characteristics sec- tion contains a graph that shows the switching frequency versus r t value. switching frequency trade-offs it is recommended that the user apply the optimal r t value given in table 1 for the input and output operating condition. system level or other considerations, however, may necessitate another operating frequency. while the ltm8052 is flexible enough to accommodate a wide range of operating frequencies, a haphazardly chosen one may result in undesirable operation under certain operating or fault conditions. a frequency that is too high can reduce efficiency, generate excessive heat or even damage the ltm8052 in some fault conditions. a frequency that is too low can result in a final design that has too much output ripple or too large of an output capacitor. switching frequency synchronization the nominal switching frequency of the ltm 8052 is determined by the resistor from the rt pin to gnd and may be set from 100 khz to 1 mhz . the internal oscillator may also be synchronized to an external clock through the sync pin . the external clock applied to t he sy nc pin
ltm8052 15 8052fa must have a logic low below 0.6 v , a logic high greater than 1.2 v and frequency between 100 khz and 1 mhz . the input frequency must be 20% higher than the frequency determined by the resistor at the rt pin . input signals outside of these specified parameters may cause erratic switching behavior and subharmonic oscillations . the sync pin must be tied to gnd if synchronization to an external clock is not required . when sync is grounded , the switching frequency is determined by the resistor at the rt pin. switching mode the ltm 8052 operates in forced continuous mode . this means that the part will not skip cycles when the load approaches zero amps . this may be particularly useful in applications where the synchronization function is used , or any time discontinuous switching is undesirable . the ltm 8052 will not operate in forced continuous mode when an input uvlo , output ovlo or minimum duty cycle violation occurs . soft-start the soft-start function controls the slew rate of the power supply output voltage during start-up. a controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the v in supply, and facilitates supply sequencing. a capacitor connected from the ss pin to gnd programs the slew rate. the capacitor is charged from an internal 11 a current source to produce a ramped output voltage. maximum output current adjust to adjust the regulated load current, an analog voltage is applied to the ctl_i pin or ctl_t pins. varying the voltage between 0 v and 1.5 v adjusts the maximum current between the minimum and the maximum current, typically 5.6 a positive and 7.7 a negative. graphs of the output current vs ctl _i and ctl _t voltages are given in the typical performance characteristics section. the ltm8052 provides a 2 v reference voltage for conveniently applying resistive dividers to set the current limit. the a pplica t ions i n f or m a t ion figure 1. setting the output current limit current limit can be set as shown in figure 1 with the following equation: i max = 7.467 ? r2 r1 + r2 amps positive current ( ) i max = ? 7.467 ? r2 r1 + r2 + 2.1 amps negative current ( ) load current derating using the ctl_t pin in high current applications, derating the maximum current based on operating temperature may prevent damage to the load. in addition, many applications have thermal limitations that will require the regulated current to be reduced based on the load and/or board temperature. to achieve this, the ltm8052 uses the ctl_t pin to reduce the effective regulated current in the load. while ctl_i programs the regulated current in the load, ctl_t can be configured to reduce this regulated current based on the analog voltage at the ctl_t pin. the load/board temperature derating is programmed using a resistor network with a temperature dependant resistance ( figure? 2). when the board/load temperature rises, the ctl_t voltage will decrease. to reduce the regulated current, the ctl_t voltage must be lower than the voltage at the ctl_i pin. v ctl_t may be higher than v ctl_i , but then it will have no effect. figure 2. load current derating vs temperature using ntc resistor ltm8052 v ref r1 2v r2 8052 f01 ctl_i or ctl_t ltm8052 v ref r ntc r x r v r v r1 r2 (option a to d) 8052 f02 ctl_t b r ntc a r ntc r x d r ntc c
ltm8052 16 8052fa a pplica t ions i n f or m a t ion figure 3. voltage regulation and overvoltage protection feedback connections voltage regulation and output overvoltage protection the ltm8052 uses the adj pin to regulate the output voltage and to provide a high speed overvoltage lockout to avoid high voltage conditions. if the output voltage exceeds 125% of the regulated voltage level (1.5v at the adj pin), the ltm8052 terminates switching and shuts down switching for a brief time before restarting. the regulated output voltage must be greater than 1.19 v and is set by the equation: v out = 1.19v 1 + 10k r adj ? ? ? ? ? ? where r adj is shown in figure 3. figure 4. uvlo configuration functionality in the specified operating range. this means that internal temperatures will exceed the 125 c absolute maximum rating when the overtemperature protection is active, possibly impairing the devices reliability. uvlo and shutdown the ltm8052 has an internal uvlo that terminates switch- ing, resets all logic, and discharges the soft-start capacitor when the input voltage is below 6 v. the ltm8052 also has a precision run function that enables switching when the voltage at the run pin rises to 1.68 v and shuts down the ltm8052 when the run pin voltage falls to 1.55 v. there is also an internal current source that provides 5.5 a of pull-down current to program additional uvlo hysteresis. for run rising, the current source is sinking 5.5 a until run = 1.68 v, after which the current source turns off. for run falling, the current source is off until the run = 1.55v, after which it sinks 5.5 a. the following equations determine the voltage divider resistors for programming the falling uvlo voltage and rising enable voltage (v ena ) as configured in figure 4. r1 = 1.55v ? r2 uvlo ? 1.55v r2 = v ena ? 1.084 ? uvlo 5.5a the run pin has an absolute maximum voltage of 6 v. to accommodate the largest range of applications, there is an internal zener diode that clamps this pin, so that it can be pulled up to a voltage higher than 6 v through a resistor that limits the current to less than 100 a. for applications where the supply range is greater than 4:1, size r2 greater than 375k. ltm8052 v out v out r adj 8052 f03 adj ltm8052 v in r2 v in r1 8052 f04 run in situations where the output of the ltm8052 is required to sink current ( that is, the load is driving current into the ltm8052 output), the module regulator will maintain voltage regulation as long as the negative current limit is not exceeded. if the current limit is exceeded, the output voltage may begin to rise. if the output voltage rises more than 125% of the target regulation voltage, the output overvoltage protection will engage, and the ltm8052 will stop switching. in this situation, the load will be free to pull up the ltm8052 output. if the voltage exceeds the ltm8052 input, an internal power diode will clamp the output to a diode drop above the input. thermal shutdown if the part is too hot, the ltm8052 engages its thermal shutdown, terminates switching and discharges the soft- start capacitor. when the part has cooled, the part automati - cally restarts. this thermal shutdown is set to engage at temperatures above the 125c absolute maximum internal operating rating to ensure that it does not interfere with
ltm8052 17 8052fa a pplica t ions i n f or m a t ion input precautions when the ltm8052 is sinking current, it maintains its output voltage regulation by power conversion, not power dissipation. this means that the energy provided to the ltm8052 is in turn delivered to its input power bus. there must be something on this power bus to accept or use the energy, or the ltm8052s input voltage will rise. left unchecked, the energy can raise the input voltage above the absolute maximum voltage rating and damage the ltm8052. in many cases, the system load on the ltm8052 input bus will be sufficient to absorb the energy delivered by the module regulator. the power required by other devices will consume more than enough to make up for what the ltm8052 delivers. in cases where the ltm8052 is the largest or only power converter, this may not be true and some means may be need to be devised to prevent the ltm8052s input from rising too high. figure 5 a shows a passive crowbar circuit that will dissipate energy during momentary input overvoltage conditions. the breakdown voltage of the zener diode is chosen in conjunction with the resistor r to set the circuits trip point. the trip point is typically set well above the maximum v in voltage under normal operating conditions. this circuit does not have a precision threshold, and is subject to both part-to-part and temperature variations, so it is not suitable for applications where high accuracy is required or large voltage margins are not available. the circuit in figure 5 b also dissipates energy during mo- mentary overvoltage conditions, but is more precise than that in figure 5 a. it uses an inexpensive comparator and the v ref output of the ltm8052 to establish a reference voltage. the optional hysteresis resistor in the comparator circuit avoids mosfet chatter. figure 5 c shows a circuit that latches on and crowbars the input in an overvoltage event. the scr latches when the input voltage threshold is exceeded, so this circuit should be used with a fuse, as shown, or employ some other method to interrupt current from the load. as mentioned, the ltm8052 sinks current by energy conversion and not dissipation. thus, no matter what protection circuit that is used, the amount of power that the protection circuit must absorb depends upon the amount of power at the input. for example, if the output voltage is 2.5v and can sink 5 a, the input protection circuit should be designed to absorb at least 7.5 w. in figures 5 a and 5b, let us say that the protection activation threshold is 30v. then the circuit must be designed to be able to dissipate 7.5w and accept 7.5w/30v = 250ma. v in zener diode r q 8052 f05a ltm8052 load current gnd v out sourcing load figure 5a. the mosfet q dissipates momentary energy to gnd. the zener diode and resistor are chosen to ensure that the mosfet turns on above the maximum v in voltage under normal operation figure 5b. the comparator in this circuit activates the q mosfet at a more precise voltage than the one shown in figure 5a. the reference for the comparator is derived from the v ref pin of the ltm8052 v in v ref 8052 f05b q ltm8052 load current gnd v out sourcing load optional hysteresis resistor + ?
ltm8052 18 8052fa a pplica t ions i n f or m a t ion figures 5 a through 5 c are crowbar circuits, which attempt to prevent the input voltage from rising above some level by clamping the input to gnd through a power device. in some cases, it is possible to simply turn off the ltm8052 when the input voltage exceeds some threshold. this is possible when the voltage power source that drives current into v out never exceeds v in . an example of this circuit is shown in figure 5 d. when the power source on the output drives v in above a predetermined threshold, the comparator pulls down on the run pin and stops switching in the ltm8052. when this happens, the input capacitance needs to absorb the energy stored within the ltm8052s internal inductor, resulting in an additional voltage rise. as shown in the block diagram, the internal inductor value is 2.2 uh. if the ltm8052 negative current limit is set to 5 a, for example, the energy that the input v in zener diode scr 8052 f05a ltm8052 load current gnd v out fuse sourcing load figure 5c. the scr latches on when the activation threshold is reached, so a fuse or some other method of disconnecting the load should be used figure 5d. this comparator circuit turns off the ltm8052 if the input rises above a predetermined threshold. when the ltm8052 turns off, the energy stored in the internal inductor will raise v in a small amount above the threshold. v in run 8052 f05d 10f ltm8052 load current gnd v out sourcing load external reference voltage + ? capacitance must absorb is 1/2 li 2 = 27.5 j. suppose the comparator circuit in figure 5 d is set to pull the run pin down when v trip = 15v. the input voltage will rise according to the capacitor energy equation: 1 2 c (v in 2 ? v trip 2 ) = 27.5j if the total input capacitance is 10 f, the input voltage will rise to: 27.5j = 1 2 10f(v in 2 ? 15v 2 ) v in = 15.2v for applications where only sourcing current ( one quadrant operation) is desired, use ltm8026.
ltm8052 19 8052fa a pplica t ions i n f or m a t ion no output current sharing the ltm8052 is a two quadrant device, able to both sink and source current to maintain voltage regulation . it is therefore not suitable for current sharing. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8052. the ltm8052 is neverthe- less a switching power supply, and care must be taken to minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see figure 6 for a suggested layout. ensure that the grounding and heat sinking are acceptable. a few rules to keep in mind are: 1. place the r adj and r t resistors as close as possible to their respective pins. 2. place the c in capacitor as close as possible to the v in and gnd connection of the ltm8052. ctl_t ctl_i v ref comp ss adj sync v in ? ? ? ? ? ? ? ????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ? ? ? ? v in 8052 f06 gnd gnd c in v out v out c out gnd thermal and interconnect vias run rt ? ? 3. place the c out capacitor as close as possible to the v out and gnd connection of the ltm8052. 4. place the c in and c out capacitors such that their ground currents flow directly adjacent or underneath the ltm8052. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8052. 6. use vias to connect the gnd copper area to the boards internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 6. the ltm8052 can benefit from the heat sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. figure 6. layout showing suggested external components, gnd plane and thermal vias.
ltm8052 20 8052fa a pplica t ions i n f or m a t ion hot plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of ltm8052. however, these capacitors can cause problems if the ltm8052 is plugged into a live input supply ( see application note 88 for a complete dis- cussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the v in pin of the ltm8052 can ring to more than twice the nominal input voltage, possibly exceeding the ltm8052s rating and damaging the part. if the input supply is poorly con- trolled or the user will be plugging the ltm8052 into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series to v in , but the most popular method of controlling input voltage overshoot is to add an electrolytic bulk capacitor to the v in net. this capacitors relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filter- ing and can slightly improve the efficiency of the circuit, though it is physically large. thermal considerations the ltm8052 output current may need to be derated if it is required to operate in a high ambient temperature. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the temperature rise curves given in the typical performance characteristics section can be used as a guide. these curves were generated by the ltm8052 mounted to a 58cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. for increased accuracy and fidelity to the actual applica- tion, many designers use finite element analysis ( fea) to predict thermal performance. to that end, page 2 of the data sheet typically gives four thermal coefficients: ja C thermal resistance from junction to ambient jcbottom C thermal resistance from junction to the bottom of the product case jctop C thermal resistance from junction to top of the product case jb C thermal resistance from junction to the printed circuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confusion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased below: ja is the natural convection junction- to- ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. jcbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient envi- ronment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. jctop is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junc- tion to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application.
ltm8052 21 8052fa figure 7. thermal resistances among module device, printed circuit board and environment 8052 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance jb is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a 2-sided, 2-layer board. this board is described in jesd 51-9. given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a module regulator. thus, none of them can be individually used to accurately predict the thermal performance of the product. likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the products data sheet. the only appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. a graphical representation of these thermal resistances is given in figure 7. the blue resistances are contained within the module device, and the green are outside. the die temperature of the ltm8052 must be lower than the maximum rating of 125 c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8052. the bulk of the heat flow out of the ltm8052 is through the bottom of the module and the lga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, result- ing in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. a pplica t ions i n f or m a t ion
ltm8052 22 8052fa v in run 510k ss ltm8052 sync 100f 330f 8052 ta02 10f v in 6v to 36v v out 3.3v 5a comp v out v ref ctl_i ctl_t rt gnd 75.0k 5.62k adj + optional input protection 36v in , 3.3v out step-down cvcc converter 36v in , ltm8052 charges tw o 2.5v series supercapacitors at 5.6a v in run 510k ss ltm8052 sync 2.5v 2.2f 2.5v 2.2f 8052 ta03 10f v in 7v to 36v v out 5v 5a comp v out v ref ctl_i ctl_t rt gnd 68.1k 3.09k 47f adj optional input protection typical a pplica t ions
ltm8052 23 8052fa 36v in , 12v out step-down cvcc converter 36v in , C5v out negative cvcc converter typical a pplica t ions v in run 510k ss ltm8052 sync 47f 120f 8052 ta04 10f v in 16v to 36v v out 12v 3.5a comp v out v ref ctl_i ctl_t rt gnd 61.9k 1.1k adj + optional input protection v in run 510k ss ltm8052 sync 100f 8052 ta05 10f v in 7v to 31v v out ?5v 3a comp v out v ref ctl_i ctl_t rt gnd 68.1k 3.09k adj optional input protection 120f +
ltm8052 24 8052fa tw o ltm8052s used to regulate positive or negative voltage (and current) across a peltier device stack tw o ltm8052s to charge and actively balance supercapacitors (or batteries) typical a pplica t ions 10f v out 2v to 8v 1.74k to 14.7k 8052 ta06 v in run ss ltm8052 sync 100f (optional) 100f 330f comp v out v ref ctl_i ctl_t rt gnd 118k adj fixed 5v 383k 10f 100f 120f v in run ss ltm8052 sync comp v out v ref ctl_i ctl_t rt gnd 68.1k 3.09k adj v in 10v to 36v peltier + + 10f 10f v out 8052 ta07 v in run ss ltm8052 sync 47f comp v out v ref ctl_i ctl_t rt gnd 90.9k 9.09k 90.9k 9.09k adj 383k 2.5v supercap 2.5v supercap 47f v in run ss ltm8052 sync comp v out v ref ctl_i ctl_t rt gnd adj v in 8.5v to 36v
ltm8052 25 8052fa package top view 4 pad ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view detail a pad 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 f g h l j k e a b c d 2 1 4 3 5678 d 0.630 0.025 ? 81x e b e e b f g notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 81 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 // bbb z z detail a dia (0.630) 81x s yxeee lga 81 0310 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? symbol a b d e e f g aaa bbb eee min 2.72 0.60 nom 2.82 0.63 15.0 11.25 1.27 12.70 8.89 max 2.92 0.66 0.15 0.10 0.05 notes dimensions total number of lga pads: 81 a lga package 81-lead (15mm 11.25mm 2.82mm) (reference ltc dwg # 05-08-1868 rev ?) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltm8052 26 8052fa p ackage descrip t ion p ackage p ho t o table 3. pin assignment table (arranged by pin number) pin id function pin id function pin id function pin id function pin id function pin id function a1 v out b1 v out c1 v out d1 v out e1 gnd f1 gnd a2 v out b2 v out c2 v out d2 v out e2 gnd f2 gnd a3 v out b3 v out c3 v out d3 v out e3 gnd f3 gnd a4 v out b4 v out c4 v out d4 v out e4 gnd f4 gnd a5 gnd b5 gnd c5 gnd d5 gnd e5 gnd f5 gnd a6 gnd b6 gnd c6 gnd d6 gnd e6 gnd f6 gnd a7 gnd b7 gnd c7 gnd d7 gnd e7 gnd f7 gnd a8 gnd b8 gnd c8 gnd d8 ctl_t e8 ctl_i f8 v ref pin id function pin id function pin id function pin id function pin id function g1 gnd C C j1 v in k1 v in l1 v in g2 gnd C C j2 v in k2 v in l2 v in g3 gnd C C j3 v in k3 v in l3 v in g4 gnd C C C C C C C C g5 gnd h5 gnd j5 gnd k5 gnd l5 gnd g6 gnd h6 gnd j6 gnd k6 gnd l6 run g7 gnd h7 gnd j7 gnd k7 gnd l7 sync g8 rt h8 comp j8 ss k8 adj l8 gnd
ltm8052 27 8052fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 3/12 modified the description section. updated the absolute maximum ratings and pin configuration sections. corrected the pin name on schematics using two ltm8052s. updated the related parts table. 1 2 24 28
ltm8052 28 8052fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0312 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltm8026 36v in , 5a step-down module regulator with adjustable current limit 6v v in 36v, 1.2v v out 24v, adjustable current limit, parallelable outputs, clk input, 11.25mm 15mm 2.82mm lga package ltm8025 36v in , 3a step-down module regulator 3.6v v in 36v, 0.8v v out 24v, clk input, 9mm 15mm 4.32mm lga package ltm8062/ ltm8062a 32v in , 2a module battery charger with maximum peak power tracking (mppt) adjustable v batt up to 14.4v (18.8v for the ltm8062a), c/10 or timer termination, 9mm 15mm 4.32mm lga package ltm8027 60v in , 4a dc/dc step-down module regulator 4.5v v in 60v, 2.5v v out 24v, 15mm 15mm 4.32mm lga package LTM4613 en55022b compliant 36v in , 8a step-down module regulator 5v v in 36v, 3.3v v out 15v, synchronizable, parallelable, 15mm 15mm 4.32mm lga package 36v in , 3.3v out step-down converter with 4.75a accurate current limit v in run ss ltm8052 sync 100f 330f v out 3.3v 4.75a 8052 ta08 comp v out v ref ctl_i ctl_t rt gnd 75k 127k 5.62k 71.5k adj 10f 510k v in 6v to 36v + optional input protection

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